Process for forming high voltage junction termination extension oxide

ABSTRACT

A process for forming a junction termination extension (JTE) oxide having reduced total oxide charge and SiO 2 —Si interface trap density parameters uses precursor densified thin oxide layers, to improve the quality of subsequently formed thicker oxide layers, and multiple anneals to remove implant damage and set geometry parameters. After formation of a first dual oxide layer, and a post-oxidation anneal, the oxide is patterned and JTE regions are implanted. Implant-based near surface crystalline damage is annealed out in a non-oxidizing ambient, and JTE dopants are partially driven into adjoining material of the substrate. A thin dense bulk precursor oxide layer is grown on the exposed JTE dopant-implanted surface portions of the substrate, followed by forming the bulk of the JTE oxide in a steam or wet oxygen atmosphere. The substrate is then annealed in a non-oxidizing ambient, to cause a further drive-in of the JTE dopants. The associated reduction in Qox and Dit improves high voltage edge stability.

FIELD OF THE INVENTION

[0001] The present invention relates in general to the manufacture ofhigh-voltage semiconductor integrated circuits, and is particularlydirected to a new and improved process for forming a junctiontermination extension (JTE) oxide that enjoys reduced total oxide charge(Qox) and SiO₂—Si interface trap density (Dit) parameters, therebyoffering improved high voltage edge stability.

BACKGROUND OF THE INVENTION

[0002] High-voltage discrete and integrated circuit devices, which arecurrently employed in a wide variety of electrical and electroniccircuit architectures, are subject to excessive electric field intensitycreated in the vicinity of a reverse-biased PN junction. Oneparticularly effective mechanism to deal with this problem has been touse a junction termination extension (JTE), as a barrier against theeffects of the electric field. In a typical architecture, the JTE deviceis passivated by a relatively thick bulk oxide layer that is formed bythe process sequence shown in FIG. 1, respective steps of which yield adevice structure shown in the associated cross-sectional diagrams ofFIGS. 2A-2F.

[0003] More particularly, as shown at step 101, the conventional processbegins by exposing the top surface of a semiconductor (silicon)substrate 1, shown in FIG. 2A, to a ‘wet’ or steam ambient, so as torapidly grow a relatively thick ubiquitous oxide layer 2, that is toserve as part of the bulk JTE oxide. As shown at step 103 and FIG. 2B,the oxide layer 2 is then patterned, etched and cleaned/rinsed to open aplurality of implant apertures 3, which expose corresponding (JTEdopant-implant) surface portions 4 in the top surface of substrate 1.

[0004] In step 105, conductivity type determining impurities 5 areimplanted through the implant apertures 3 of the oxide layer 2, forminga plurality of JTE surface regions shown at 6 in FIG. 2C. This implantstep introduces unwanted near-surface pockets of crystalline damage 7 inthe vicinity of the top surface of the silicon substrate. In order toremove this crystalline damage and prevent stacking fault formation, atstep 107, a wet or stream screen oxide layer 8 is rapidly grown directlyon the JTE surface regions 6, as shown in FIG. 2D. Unfortunately,because the oxide layer 8 is grown rapidly and directly upon theimplanted surface of the silicon, it is of relatively poor quality, andcan be expected to negatively impact the quality of any subsequentlyformed oxide.

[0005] Following formation of the screen oxide layer 8, the device issubjected to a dopant drive-in step 109, which causes the dopant of theimplanted regions 6 to diffuse into the surrounding substrate, andessentially define the JTE structure, as shown at 6′ in FIG. 2E.Although some additional dopant diffusion will occur during subsequentoxidation, the bulk of the dopant drive-in is completed in this step.The JTE oxide process is completed by performing a further rapid steamor wet oxidation step 111, which fills in the implant apertures 3 withoxide 9 and results in the JTE structure shown in FIG. 2F.

[0006] Because each of the oxide layers formed in the process of FIGS. 1and 2, particularly those overlying the implanted regions, are grownrapidly in a wet or stream atmosphere, they are of relatively lowdensity. As a result they facilitate segregation or out-diffusion ofdopants into the oxide, and reduce the quality of any oxide grownthereon. This has the unwanted effect of allowing the total oxide charge(Qox) and SiO₂—Si interface trap density (Dit) to increase, whichdegrades high voltage stability.

SUMMARY OF THE INVENTION

[0007] In accordance with the present invention, the above-referencedshortcomings of conventional JTE oxide formation are effectivelyobviated by employing precursor densified thin oxide layers to improvethe quality of subsequently formed thicker oxide layers, and performingmultiple anneals in a dry or non-oxidizing atmosphere to remove implantdamage and to set finalized geometry parameters. The use of such anatmosphere for post JTE oxidation annealing substantially lowers Qox andDit.

[0008] In order to ensure precise control of subsequent oxide formation,a relatively thin and dense precursor oxide layer is ubiquitously grownon the surface of a silicon substrate in a dry oxygen ambient. Thethickness of the oxide layer is increased in a steam or wet oxygenatmosphere, causing the growth of a relatively thick silicon dioxidelayer. Because the thin precursor oxide layer is highly densified, itincreases the density and quality of the thick oxide layer.

[0009] A post-oxidation anneal is then performed in a dry ambient ornon-oxidizing atmosphere, which substantially reduces Qox and Dit. Theoxide then masked and etched to form a plurality of dopant implantapertures in the oxide layer. JTE dopants are then implanted through theimplant apertures of the oxide layer, forming a plurality ofconductivity-modifying semiconductor JTE regions that extend to aprescribed implant depth from the top surface of the silicon substrate.

[0010] In order to remove near surface crystalline damage caused by theimplant, the substrate is annealed in a non-oxidizing or inert gasambient. The non-oxidizing atmosphere of the annealing step preventsoxidation of the top surface of the substrate from which the JTE regionsextend, and thereby avoids negatively impacting subsequent oxideformation. A dry oxide ambient cannot be used to anneal out thecrystalline damage during this step, since formation of a highly denseoxide layer may cause the formation of oxidation-induced stackingfaults. The JTE dopants are then partially driven away from thenear-surface portions into adjoining material of the substrate, toprevent segregation of the dopant into the oxide that will besubsequently grown.

[0011] A relatively thin and highly densified bulk oxide precursor layeris then grown on the exposed JTE dopant-implanted surface portions ofthe substrate to ensure precise control of subsequent oxide formation.The bulk of the JTE oxide is then formed in a steam or wet oxygenatmosphere.

[0012] After the bulk oxide has been grown to its desired thickness, thesubstrate is annealed in a non-oxidizing or inert gas ambient, to causea further drive-in of the JTE dopants. The dry or non-oxidizingatmosphere of the post JTE oxidation annealing step substantially lowersQox and Dit. The reduction in Qox and Dit (and thereby the extent towhich high voltage edge stability is improved) may be determined bycarrying out conventional capacitance-voltage and associated electricalparameter measurements, such as those commonly employed for MOScapacitor structures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 shows the process steps of a conventional JTE oxideprocess;

[0014] FIGS. 2A-2F are diagrammatic sectional views of a JTEsemiconductor structure at respective steps of the process of FIG. 1;

[0015] FIGS. 3A-3I are diagrammatic sectional views of a JTEsemiconductor structure at respective steps of the JTE oxide process ofthe present invention; and

[0016]FIG. 4 shows the sequence of steps of the JTE oxide formationprocess of the invention.

DETAILED DESCRIPTION

[0017] The process through which a high voltage junction terminationextension oxide is formed on a semiconductor substrate/wafer inaccordance with a preferred embodiment of the present invention will nowbe described with reference to the cross-sectional diagrams of FIGS.3A-3I, that show the state of the device at respective steps of theprocessing flow sequence of FIG. 4.

[0018] As shown in FIGS. 3A and 3B, the oxidation formation processbegins by forming a relatively thick oxide layer 10 (e.g., 800Angstroms) on a top surface 21 of a clean or epitaxial semiconductorsubstrate 20, such as a silicon substrate of a first conductivity type(e.g., N type as a non-limiting example). In order to ensure precisecontrol of subsequent oxide formation, in step 401, oxide layer 10 isformed by first slowly growing a relatively thin and dense precursoroxide layer, such as silicon dioxide 12 (FIG. 3A) in a dry oxygen (O₂)ambient, for example, at a temperature of 900° C., for 120 minutes, to afirst thickness (e.g., 300 Angstroms).

[0019] Next, in step 403, the thickness of the silicon dioxide layer 10is increased, by introducing steam (e.g., at a temperature on the orderof 1050° C.) or a wet O₂ atmosphere (at a temperature of 1050° C.), for120 minutes, causing the growth of a relatively thick silicon dioxidelayer 14 at the silicon surface and incorporating therein the thin denseoxide layer 12, to a thickness on the order of 80000 Angstroms, as shownin FIG. 3B. Because the thin precursor oxide layer 12 is a highlycompact oxide layer, it increases the density and quality of the thickoxide layer 14, relative to the oxide layer rapidly formed by the priorart process described previously.

[0020] Next, as shown at step 405, a post-oxidation anneal is performedin a dry ambient or non-oxidizing atmosphere, which serves tosubstantially reduce Qox and Dit. For this purpose, the anneal may becarried out at a temperature on the order of 50° C. greater than thesteam oxidation temperature (or 1100° C. in the present example), for 30minutes, in an N₂ ambient. The oxide-coated wafer is then masked, etchedand cleaned/rinsed in a conventional manner in step 407, to provide atleast one (e.g., a plurality of) implant apertures 18 in the oxide layer10, which thereby selectively expose corresponding (JTE dopant-implant)surface portions 23 in the top surface 21 of the substrate 20, as shownin FIG. 3C.

[0021] In step 409, using a conventional implant operation, such as thatdescribed previously, conductivity type determining impurities 19 (e.g.,P-type in the present example) are introduced (implanted) through theimplant apertures 18 of the oxide layer 10, so as to form a plurality of(P-type) conductivity-modifying semiconductor (JTE) regions 25 thatextend to a prescribed implant depth from the top surface 21 of thesubstrate 20, as shown in FIG. 3D. As described previously, this implantstep causes crystalline damage in those portions 26 of the JTE regions25 adjacent to the surface 21, which must be removed to prevent stackfault formation.

[0022] For this purpose, at step 411, the substrate is annealed in anon-oxidizing or inert gas ambient, such as but not limited to Ar, H₂/N₂forming gas, N₂, and the like, to repair the displaced lattice sites,resulting in the structure of FIG. 3E. As a non-limiting example, thisanneal may be carried out at a temperature on the order of 800° C., fora period of 20 minutes. The non-oxidizing atmosphere of the annealingstep prevents oxidation of the surface portions 23 of the top surface 21of the substrate 20 from which the JTE regions extend, and therebyavoids impacting subsequent oxide formation. A dry oxide ambient cannotbe used to anneal out the crystalline damage during this step, since theformation of a highly dense oxide layer may cause the formation ofoxidation-induced stacking faults.

[0023] In step 413, a partial drive-in of the conductivity typedetermining JTE dopants in regions 25 away from the near-surfaceportions into adjoining (surrounding) material of the semiconductorsubstrate 20 is performed, resulting in the expanded region structure25′ shown in FIG. 3F. This partial drive-in serves to preventsegregation of the dopant into the oxide that will be subsequentlygrown. The respective time and temperature parameters for this step maybe on the order of 160 minutes at 1200° C. The less than total dopantdrive-in during this step conserves thermal budget, providing forsubstantial annealing time after the thickness of JTE termination oxideis finalized.

[0024] Next, as shown in FIG. 3G, and at step 415, a relatively thin andhighly densified bulk precursor oxide layer 30 is grown on the exposedJTE dopant-implanted surface portions 23 of the top surface 21 of thesubstrate 20, in a dry O₂ ambient, for example, at a temperature of1050° C., for 45 minutes, to a thickness on the order of 600 Angstroms.Like the thin precursor oxide layer 12 formed in step 401, the densifiedbulk precursor oxide layer 30 ensures precise control of subsequent bulkoxide formation.

[0025] Following the formation of the thin precursor oxide layer 30within the implant apertures 18, at step 417 the bulk of the JTE oxideis formed by introducing steam (e.g., at a temperature on the order of1050° C.) or a wet O₂ atmosphere (at a temperature of 1050° C.), for 170minutes, causing the growth of a relatively thick silicon dioxide layer32 on the surface of the silicon, and incorporating the thin dense oxidelayer 30, for example to a thickness on the order of one micron, asshown in FIG. 3H. Again since bulk precursor oxide layer 30 is highlycompact and densified, it increases the density and quality of the thickJTE oxide layer 32. During step 417, the thickness of dense oxide layer30 is not significantly altered, as its thickness and density make it asubstantially diffusion-limited film.

[0026] Once the bulk oxide 32 has been grown to its desired thickness,the substrate is again annealed in a non-oxidizing or inert gas ambient,such as but not limited to Ar, H₂/N₂ forming gas, N₂, and the like,referenced above, to effect a further drive-in of the conductivity typedetermining JTE dopants—forming regions 25″, shown in the structure ofFIG. 3I. As a non-limiting example, this final, post-JTE oxidationanneal may be carried out at a temperature on the order of 1100° C., fora period of 30 minutes. The ‘dry’ or non-oxidizing atmosphere of thepost JTE oxidation annealing step substantially lowers Qox and Dit. Theextent to which high voltage edge stability is improved, as representedby a reduction in Qox and Dit, may be determined by carrying outconventional capacitance-voltage and associated electrical parametermeasurements, such as those commonly employed for MOS capacitorstructures.

[0027] As will be appreciated from the foregoing description, theabove-referenced shortcomings of conventional JTE oxide formation areeffectively obviated by employing precursor densified thin oxide layersto improve the quality of subsequently formed thicker oxide layers, andperforming multiple anneals in a dry or non-oxidizing atmosphere toremove implant damage and to set finalized geometry parameters. The useof such an atmosphere for post JTE oxidation annealing substantiallylowers Qox and Dit.

[0028] While we have shown and described an embodiment in accordancewith the present invention, it is to be understood that the same is notlimited thereto but is susceptible to numerous changes and modificationsas are known to a person skilled in the art, and we therefore do notwish to be limited to the details shown and described herein, but intendto cover all such changes and modifications as are obvious to one ofordinary skill in the art.

What is claimed:
 1. A method of manufacturing a semiconductor devicecomprising the steps of: (a) introducing conductivity type determiningimpurities into a selected surface portion of a semiconductor substrate,so as to form a region containing near-surface region crystallinedamage; (b) annealing the structure resulting from step (a) in anon-oxidizing atmosphere to reduce said near-surface region crystallinedamage; (c) performing partial drive-in of said conductivity typedetermining impurities away from said near-surface region to material ofsaid semiconductor substrate adjoining said region; (d) forming aninsulator layer upon said region; and (e) annealing the structureresulting from step (d) in a non-oxidizing atmosphere and effecting afurther drive-in of said conductivity type determining impurities tomaterial of said semiconductor substrate adjoining said region.
 2. Amethod according to claim 1 , wherein step (d) comprises forming saidinsulator layer to a first thickness upon said region in a firstambient, and thereafter increasing the thickness of said insulator in asecond ambient.
 3. A method according to claim 2 , wherein step (d)comprises forming a first oxide layer to said first thickness upon saidregion in a first oxide ambient, and thereafter forming, in a secondoxide ambient, a second oxide layer, that incorporates therein saidfirst oxide layer, to a second thickness greater than said firstthickness.
 4. A method according to claim 1 , wherein step (a) comprisesimplanting said conductivity type determining impurities into saidselected surface portion of a semiconductor substrate, so as to formsaid region containing near-surface region crystalline damage.
 5. Amethod according to claim 4 , wherein step (a) includes the precursorsteps of forming a relatively thin and dense precursor oxide layer onsaid substrate in a dry oxygen ambient, growing a relatively thick oxidelayer that incorporates therein said precursor oxide layer, conducting apost-oxidation anneal in a non-oxidizing atmosphere, so as tosubstantially reduce total oxide charge (Qox) and SiO₂—Si interface trapdensity (Dit), and patterning said oxide layers to form a plurality ofJTE conductivity type determining impurity implant apertures therein. 6.A method according to claim 3 , wherein step (d) comprises growing saidfirst oxide layer as a relatively thin and highly densified bulk oxideprecursor layer, and growing said second oxide layer as a bulk JTE oxidein a steam or wet oxygen atmosphere.
 7. A method of manufacturing ajunction termination extension (JTE) semiconductor device comprising thesteps of: (a) forming a first densified relatively thin and denseprecursor oxide layer on a semiconductor substrate; (b) growing on saidsemiconductor substrate a second relatively thick oxide layer thatincorporates therein said first oxide layer; (c) performing apost-oxidation anneal of the structure resulting from step (b), so as toreduce total oxide charge (Qox) and oxide-substrate interface trapdensity (Dit) parameters; (d) patterning said first and said oxidelayers and implanting JTE dopants through implant apertures of thepatterned oxide layers, thereby forming a plurality of JTE regions thatextend to a prescribed implant depth from the top surface of saidsubstrate; (e) annealing said substrate in a non-oxidizing atmosphere toremove near surface crystalline damage caused by implantation of JTEdopants, and effecting a partial drive-in of implanted JTE dopants; (f)growing a third, relatively thin and highly densified bulk precursoroxide layer on exposed JTE-implanted surface portions of said substrate;(g) growing a fourth, relatively thick bulk oxide layer on said thirdoxide layer; and (h) annealing said substrate in a non-oxidizing gasambient, so as to further drive-in said JTE dopants, and reduce saidtotal oxide charge (Qox) and oxide-substrate interface trap density(Dit) parameters.
 8. A method according to claim 7 , wherein step (a) iscarried out in a dry oxygen ambient, and step (b) is carried out in awet or stream atmosphere.
 9. A method according to claim 7 , whereinstep (c) is carried out in a dry ambient or non-oxidizing atmosphere.